This application incorporates by reference Taiwan application Serial No. 89116291, filed Aug. 11, 2000.
1. Field of the Invention
The invention relates in general to a Viterbi detector for extending tolerable extent of direct current (DC) bias, and more particularly to a Viterbi detector, used in a partial response maximum likelihood (PRML) signal processing apparatus, for extending the tolerable extent of the DC bias.
2. Description of the Related Art
There are many approaches to the storage of information code in a recording medium. For the increasing the data access density, partial response maximum likelihood (PRML) signal processing is widely used in optical disk systems.
In the process of transmitting signals, when the channel bandwidth is lower than the bandwidth of the signals transmitted in the channel, inter-symbol interference (ISI) occurs in adjacent bits of the signals in the receiving end. When ISI is serious, it may cause jitter. As the recording density of optical disks increases, jitter caused by ISI becomes more serious, increasing the difficulty in phase-locking. For overcoming this phenomenon, the principle of partial response (PR) channel is applied. In PRML signal processing, the channel response is appropriately equalized in a channel response in terms of a PR polynomial. In this way, ISI is constrained and is in an expectable characteristic, resulting in reduction of jitter when ISI occurring. Thus, the performance of phase-locking is improved. In other words, PRML is potentially a technique of improving the recording density of optical disks.
Referring to FIG. 1, it illustrates a PRML signal processing apparatus in block diagram form. In FIG. 1, modulated information code E is first inputted into a return-to-zero inversion (NRZI) circuit 102. The modulated information code signal E is then processed by an exclusive-OR gate 104 and a delay element 106 of the NRZI circuit 102, resulting in an output signal F of the NRZI circuit. After that, the output signal F of the NRZI circuit is written to a recording medium 108, such as an optical disk. In addition, PR(1, 2, 1) equalization of the output signal F of the NRZI circuit is performed, where the minimum code reversal distance xcex4=2.
Referring now to FIG. 2, it illustrates the waveforms of the signals involved in FIG. 1 including the information code signal E, output signal F of the NRZI circuit, reproduce signal G, output signal J of the PR equalizer and output signal Z of the Viterbi detector, and the corresponding pits on the optical disk. In FIG. 2, the bit sequence in (a) corresponds to an example the information code signal E while the bit sequence in (b) illustrates the corresponding output signal F of the NRZI circuit. When the information code signal E has a signal level change of rising edge, the signal Z has a signal level change of itself as well; otherwise, the signal level of the signal Z remains unchanged. The signal in (c) is the LD driving signal produced according to the signal F and is used for controlling a LD (not shown in Figures) to perform write operation on the optical disk. Illustration in (d) is to show the pits on the optical disk which the LD performs the write operation on. The signal of (e) is the reproduce signal G corresponding to the data read from the optical disk by using the optical head. The signal of (f) is the output signal J of the PR equalizer 110 after the PR(1, 2, 1) process. And the signal of (g) is the output signal Z of the Viterbi detector 112 obtained after processing the signal J. The PR equalizer 110 and Viterbi detector 112 are called a reproduction signal processing unit 114.
In FIG. 2, when the signal F is in a 1 state, the LD driving signal is in the high level. Accordingly, a pit is produced on the optical disk. The reproduction signal processing unit 114 is used for generating the signal Z by the Viterbi detector using the reproduce signal G. The signal Z is theoretically identical to the information code signal E.
Referring to FIG. 3, it illustrates the Viterbi detector 112 in FIG. 1 in block diagram form. The Viterbi detector includes a branch metric calculation circuit 302, an add-compare-and-select (ACS) circuit 304 and a path memory unit 306. The branch metric calculation circuit 302 is for receiving the output signal J of the PR equalizer and calculating the values B0001, B0002, B0011, B0111, B1001, B1101, B1111, and B1112, called the branch metrics. The ACS circuit 304 is for outputting a path memory control signals H000 and H111 based on the branch metrics above. The path memory unit 306 is controlled by the path memory control signals H000 and H111, outputting the output signal Z of the Viterbi detector.
FIG. 4 is a block diagram of the branch metric calculation circuit 302 in FIG. 3. The branch metric calculation circuit 302 includes four subtractors 402, four multiplier 404, and four registers 406. In FIG. 4, the subtractors 402 respectively calculate J-0, J-0.25, J-0.75, and J-1. Next, the outputs of the subtractors are respectively processed by the multiplers 404 for obtaining the respective squares. Then, the four squares of the difference of the PR equalizer output signal J and four equalization-aimed values {0, 0.25, 0.75, 1} are stored in the delay units 406 respectively. The branch metric calculation circuit 302 outputs the branch metrics B0001, B0002, B0011, B0111, B1001, B1101, B1111, and B1112 respectively. For each point of time, the branch metrics are as follows:
B0001=B0002=(0xe2x88x92J)2, 
B0011=B1001=(0.25xe2x88x92J)2, 
B0111=B1101=(0.75xe2x88x92J)2, 
and
B1111=B1112=(1.0xe2x88x92J)2. 
Referring now to FIG. 3, the branch metrics are inputted into the ACS circuit 304. The branch metrics represent the degree and nearness of the PR equalizer output signal J obtained from the PR(1, 2, 1) equalization of the reproduce signal, and the ideal PR(1, 2, 1) equalization signal.
The ACS circuit 304 uses six path metrics, P000, P001, P011, P100, P110, and P111, and the initial values of them are set to zero. The ACS circuit 304 derives the path metric at time t from the path metric and performs comparison of P000(t)+B0001(t) and P100(t)+B1002(t) as well as P011(t)+B1111(t) and P111(t)+B1112(t). From this, the ACS determines and outputs the path control signals H000(t) and H111(t).
Further, the ACS circuit 304 updates the values of the path metrics P000(t+1), P001(t+1), P011(t+1), P100(t+1), P110(t+1), and P111(t+1) according to the following expressions:
P000(t+1)=min{P000(t)+B0001(t), P100(t)+B0002(t)}, 
P001(t+1)=P000(t)+B0011(t), 
P011(t+1)=P001(t)+B0111(t), 
P100(t+1)=P110(t)+B1001(t), 
P110(t+1)=P111(t)+B1101(t), 
and
P111(t+1)=min{P011(t)+B1111(t) and P111(t)+B1112(t)}. 
The path control signal H000 and H111 are respectively inputted into the path memory unit 306. The path memory unit 306 stores signal level transition patterns of the output signal J of the PR equalizer corresponding to each point of time in the form of a trellis. In addition, the path memory unit 306 only outputs binary signals. Moreover, when the PR equalizer""s output signal J has noise, the Viterbi detector 112 selects the nearest signal level transition pattern according to the path control signals H000 and H111 for each point of time and stores the selected transition patterns in the path memory unit 306.
In another aspect, path metrics corresponds to the cost of a transition from the state at time txe2x88x921 to the state at time t. In this way, the Viterbi detector 112 is to calculate the cost of each path through the branch metrics, resulting in a path control signal (H000, H111) with the minimum cost. By the path control signal (H000, H111), the Viterbi detector 112 selects the required path to be stored in the path memory unit 306, obtaining the Viterbi detector""s output signal Z.
In FIG. 2, it employs the ideal PR equalizer""s output signal J for illustration, where the DC bias of the signal is set to zero. However, in some cases, the DC bias of the PR equalizer""s output signal may be non-zero. In this way, the system performance is reduced.
Referring to FIGS. 5A-5C, they illustrates waveforms of a LD driving signal and the corresponding PR equalizer""s output signal J with DC bias. FIG. 5A is the waveform diagram of the LD driving signal while FIG. 5B is the ideal PR equalizer""s output signal J. FIG. 5C is the PR equalizer""s output signal in practice.
Take the LD driving signal shown in FIG. 5A as an example, where the signal has many times of being in a high or low state for the time of 11T or 3T and T is the period of the clock. As shown in FIG. 5B, the corresponding PR equalizer""s output signal J ideally has a constant DC level at any time. However, as shown in FIG. 5C, the DC level of the PR equalizer""s output signal varies with the pattern of the LD driving signal. To be specific, when the LD driving signal is in a state for the time of 11T, the corresponding signal J in FIG. 5C has a DC level denoted as DCxe2x80x9411T. When the LD driving signal is in a state for the time of 3T, the DC level changes to another value denoted as DCxe2x80x943T. However, for the DC level, the tolerance of the signal being in a state for 11T is greater than that for 3T. For the system to detect the signal when a state of the signal is lasting for 3T, the DC level of DCxe2x80x943T is defined as the DC level of the signal in the system. In this case, a fixed DC bias occurs when the signal is in a state for 11T.
For illustrating the effects and the problems along with the DC bias, referring now to FIGS. 6A-6C, they illustrate another circuit structure and corresponding waveforms when DC bias occurs. As shown in FIG. 6A, a circuit structure for reproduction signal processing includes an analog-to-digital (A/D) converter 602 and the PR equalizer 110, and the Viterbi detector 112. In FIG. 6A, the A/D converter 602 is included and coupled to the PR equalizer 110. In this way, the PR equalizer is capable of performing digital or analog signal processing. Referring to FIG. 6B, it illustrates a waveform of the input signal P of the A/D converter 602. In FIG. 6B, the extent of the signal P is R1 while the operating extent of the A/D converter 602 is R2. If the extent R1 exceeds the operating extent R2, the output signal Q of the A/D converter 602 is illustrated in FIG. 6C. In FIG. 6C, the waveform of the signal Q near the peaks is truncated, leading to the DC bias occurs in the signal Q. As shown in FIG. 6C, the DC level of the signal P is DC_P while the DC level of the signal Q is DC_Q. Thus, the difference of DC_P and DC_Q is the DC bias of the signal Q. In this way, the signal Q has DC bias so that the output signal J of the equalizer has DC bias as well.
However, when the DC bias of the PR equalizer""s output signal J is not zero, the performance of the Viterbi detector 112 will be greatly affected. In this way, in the analysis of the effect of the PR equalizer""s output signal J with DC bias on the performance of the Viterbi detector 112, the bit error rate (BER) and signal-to-noise ratio (SNR) of the Viterbi detector""s are employed.
It can be known that, according to the simulation where the SNR is a constant, the greater the DC bias is, the greater the BER is. Therefore, when the DC bias increases, the performance of the Viterbi detector decreases. In another situation that the system requires the BER is less than a fixed value, when the system SNR increases, the DC bias of the PR equalizer""s output signal that the system can tolerate also decreases.
For resolving the DC bias"" negative effects on the Viterbi detector""s performance, the conventional method is to subtract the DC bias from the PR equalizer""s output signal J and the result of this subtraction is then inputted into the Viterbi detector 112. However, in the case of DC bias occurring inside the system, it is more difficult to completely remove the DC bias from the PR equalizer""s output signal. Therefore, the performance of the Viterbi detector 112 lowers.
It is therefore an object of the invention to provide a Viterbi detector for extending tolerable extent of DC bias. By adding a fixed value to a reference level or subtracting a fixed value from the reference level, the tolerable extent of the DC bias of the input signal is increased. According to the invention, the effect can be achieved by using a control circuit including registers.
According to the object of the invention, it provides a Viterbi detector for extending the tolerable extent of the direct current (DC) bias, for receiving a first signal. The Viterbi detector includes a first and second branch metric calculation circuits, a first and second add-compare-select (ACS) circuits, a first and second path memory units, and a control circuit. The first branch metric calculation circuit is for receiving the first signal and an equalization-aimed value increased by xcex1% and outputting a first set of branch metrics. The second branch metric calculation circuit is for receiving the first signal and an equalization-aimed value decreased by xcex1% and outputting a second set of branch metrics. The first ACS circuit is for receiving the first set of branch metrics and outputting a first set of path control signals and a first set of path metrics. The second ACS circuit is for receiving the second set of branch metrics and outputting a second set of path control signals and a second set of path metrics. The first path memory unit is for receiving the first set of path control signals and outputting a third signal while the second path memory unit is for receiving the second set of path control signals and outputting a fourth signal. The control circuit is for receiving the first set of path metrics and selecting a first path metric from the first set of path metrics, and for receiving the second set of path metrics and selecting a second path metric from the second set of path metrics. When the first path metric is less than the second path metric, the control circuit selects the third signal as the output of the Viterbi detector. When the second path metric is less than the first path metric, the control circuit selects the fourth signal as the output of the Viterbi detector. The first path metric is the minimum value of the first set of path metrics, and the second path metric is the minimum value of the second set of path metrics.
According to the object of the invention, it provides a Viterbi detector for extending the tolerable extent of the direct current (DCC) bias, for receiving a first signal. The Viterbi detector includes a first and second branch metric calculation circuits, a first and second add-compare-select (ACS) circuits, a path memory unit, and a control circuit. The first branch metric calculation circuit is for receiving the first signal and an equalization-aimed value increased by xcex1% and outputting a first set of branch metrics. The second branch metric calculation circuit is for receiving the first signal and an equalization-aimed value decreased by xcex1% and outputting a second set of branch metrics. The first ACS circuit is for receiving the first set of branch metrics and outputting a first set of path control signals and a first set of path metrics. The second ACS circuit is for receiving the second set of branch metrics and outputting a second set of path control signals and a second set of path metrics. The path memory unit is for outputting an output signal of the Viterbi detector. The control circuit is for receiving the first set of path metrics and selecting a first path metric from the first set of path metrics, and for receiving the second set of path metrics and selecting a second path metric from the second set of path metrics. When the first path metric is less than the second path metric, the control circuit selects the first set of path metrics and outputs the first set of path metrics to the path memory unit. When the second path metric is less than the first path metric, the control circuit selects the second set of path metrics and outputs the second set of path metrics to the path memory unit. The first path metric is the minimum value of the first set of path metrics, and the second path metric is the minimum value of the second set of path metrics.
According to the object of the invention, it provides a Viterbi detector for extending the tolerable extent of the direct current (DC) bias, for receiving a first signal. The Viterbi detector includes a branch metric calculation circuit, a add-compare-select (ACS) circuit, a path memory unit, and a control circuit. The branch metric calculation circuit is for alternately receiving an equalization-aimed value increased by xcex1% or an equalization-aimed value decreased by xcex1% and alternately outputting a first set of branch metrics or a second set of branch metrics. The first set of branch metrics corresponds to the equalization-aimed value increased by xcex1% and the second set of branch metrics corresponds to the equalization-aimed value decreased by xcex1%. The ACS circuit is for alternately receiving the first set of branch metrics or the second set of branch metrics and for alternately outputting a first set of path control signals and a first set of path metrics, or a second set of path control signals and a second set of path metrics. The path memory unit is for outputting an output signal of the Viterbi detector. The control circuit is for controlling the alternate receive and output operations in the branch metric calculation circuit and the ACS circuit, for receiving the first set of path metrics and selecting a first path metric from the first set of path metrics, and for receiving the second set of path metrics and selecting a second path metric from the second set of path metrics. When the first path metric is less than the second path metric, the control circuit selects the first set of path metrics and outputs the first set of path metrics to the path memory unit. When the second path metric is less than the first path metric, the control circuit selects the second set of path metrics and outputs the second set of path metrics to the path memory unit. The first path metric is the minimum value of the first set of path metrics, and the second path metric is the minimum value of the second set of path metrics.